Motion estimation and CABAC VLSI co-processors for real-time high-quality H.264/AVC video coding

Real-time and high-quality video coding is gaining a wide interest in the research and industrial community for different applications. H.264/AVC, a recent standard for high performance video coding, can be successfully exploited in several scenarios including digital video broadcasting, high-definition TV and DVD-based systems, which require to sustain up to tens of Mbits/s. To that purpose this paper proposes optimized architectures for H.264/AVC most critical tasks, Motion estimation and context adaptive binary arithmetic coding. Post synthesis results on sub-micron CMOS standard-cells technologies show that the proposed architectures can actually process in real-time 720 × 480 video sequences at 30 frames/s and grant more than 50 Mbits/s. The achieved circuit complexity and power consumption budgets are suitable for their integration in complex VLSI multimedia systems based either on AHB bus centric on-chip communication system or on novel Network-on-Chip (NoC) infrastructures for MPSoC (Multi-Processor System on Chip

Real-Time and High-Accuracy Arctangent Computation Using CORDIC and Fast Magnitude Estimation

This paper presents an improved VLSI (Very Large Scale of Integration) architecture for real-time and high-accuracy computation of trigonometric functions with fixed-point arithmetic, particularly arctangent using CORDIC (Coordinate Rotation Digital Computer) and fast magnitude estimation. The standard CORDIC implementation suffers of a loss of accuracy when the magnitude of the input vector becomes small. Using a fast magnitude estimator before running the standard algorithm, a pre-processing magnification is implemented, shifting the input coordinates by a proper factor. The entire architecture does not use a multiplier, it uses only shift and add primitives as the original CORDIC, and it does not change the data path precision of the CORDIC core. A bit-true case study is presented showing a reduction of the maximum phase error from 414 LSB (angle error of 0.6355 rad) to 4 LSB (angle error of 0.0061 rad), with small overheads of complexity and speed. Implementation of the new architecture in 0.18 µm CMOS technology allows for real-time and low-power processing of CORDIC and arctangent, which are key functions in many embedded DSP systems. The proposed macrocell has been verified by integration in a system-on-chip, called SENSASIP (Sensor Application Specific Instruction-set Processor), for position sensor signal processing in automotive measurement application

A high throughput hardware architecture for parallel recursive systematic convolutional encoders

During the last years, recursive systematic convolutional (RSC) encoders have found application in modern telecommunication systems to reduce the bit error rate (BER). In view of the necessity of increasing the throughput of such applications, several approaches using hardware implementations of RSC encoders were explored. In this paper, we propose a hardware intellectual property (IP) for high throughput RSC encoders. The IP core exploits a methodology based on the ABCD matrices model which permits to increase the number of inputs bits processed in parallel. Through an analysis of the proposed network topology and by exploiting data relative to the implementation on Zynq 7000 xc7z010clg400-1 field programmable gate array (FPGA), an estimation of the dependency of the input data rate and of the source occupation on the parallelism degree is performed. Such analysis, together with the BER curves, provides a description of the principal merit parameters of a RSC encoder

Hard macrocells for DC/DC converter in automotive embedded mechatronic systems

A novel configurable DC/DC converter architecture, to be integrated as hard macrocell in automotive embedded systems, is proposed in the paper. It aims at realizing an intelligent voltage regulator. With respect to the state of the art, the challenge is the integration into an automotive-qualified chip of several advanced features like dithering of switching frequency, nested control loops with both current and voltage feedback, asynchronous hysteretic control for low power mode, slope control of the power FET gate driver, and diagnostic block against out-of-range current or voltage or temperature conditions. Moreover, the converter macrocell can be connected to the in-vehicle digital network, exchanging with the main vehicle control unit status/diagnostic flags and commands. The proposed design can be configured to work both in step-up and step-down modes, to face a very wide operating input voltage range from 2.5 to 60 V and absolute range from −0.3 to 70 V. The main target is regulating all voltages required in the emerging hybrid/electric vehicles where, besides the conventional 12 V DC bus, also a 48 V DC bus is present. The proposed design supports also digital configurability of the output regulated voltage, through a programmable divider, and of the coefficients of the proportional-integrative controller inside the nested control loops. Fabricated in 0.35 μm CMOS technology, experimental measurements prove that the IC can operate in harsh automotive environments since it meets stringent requirements in terms of electrostatic discharge (ESD) protection, operating temperature range, out-of-range current, or voltage condition

SHINe: Simulator for satellite on-board high-speed networks featuring SpaceFibre and SpaceWire protocols

The continuous innovation of satellite payloads is leading to an increasing demand of data-rate for on-board satellite networks. In particular, modern optical detectors generate and need to transfer data at more than 1 Gbps, a speed that cannot be satisfied with standardized technologies such as SpaceWire. To fill this gap, the European Space Agency (ESA) is supporting the development of a new high-speed link standard, SpaceFibre. SpaceFibre provides a data-rate higher than 6.25 Gbps, together with the possibility to use multiple Virtual Channels running over the same physical link, each one configurable with flexible Quality of Service parameters. These features make a SpaceFibre network very appealing but also complex to set up in order to achieve the desired end-to-end requirements. To help this process, a Simulator for HIgh-speed Network (SHINe) based on the open-source toolkit OMNeT++ has been developed and is presented in this paper. It supports the simulation of SpaceFibre and SpaceWire protocols in order to help both the final steps of the standardization process and the system engineers in the setup and test of new networks. SHINe allows to precisely simulate common network metrics, such as latency and bandwidth usage, and it can be connected to real hardware in a Hardware-in-the-Loop configuration

A robust ransac-based planet radius estimation for onboard visual based navigation

Individual spacecraft manual navigation by human operators from ground station is expected to be an emerging problem as the number of spacecraft for space exploration increases. Hence, as an attempt to reduce the burden to control multiple spacecraft, future missions will employ smart spacecraft able to navigate and operate autonomously. Recently, image-based optical navigation systems have proved to be promising solutions for inexpensive autonomous navigation. In this paper, we propose a robust image processing pipeline for estimating the center and radius of planets and moons in an image taken by an on-board camera. Our custom image pre-processing pipeline is tailored for resource-constrained applications, as it features a computationally simple processing flow with a limited memory footprint. The core of the proposed pipeline is a best-fitting model based on the RANSAC algorithm that is able to handle images corrupted with Gaussian noise, image distortions, and frame drops. We report processing time, pixel-level error of estimated body center and radius and the effect of noise on estimated body parameters for a dataset of synthetic images

Modifications of midpalatal sutural density induced by rapid maxillary expansion: A low-dose computed-tomography evaluation.

INTRODUCTION: The aim of this study was to evaluate the density of the midpalatal suture as assessed by low-dose computed tomography (CT) before rapid maxillary expansion (RME) (T0), at the end of active expansion (T1), and after a retention period of 6 months (T2). METHODS: The study sample comprised 17 prepubertal subjects (mean age, 11.2 years) with constricted maxillary arches and unilateral or bilateral posterior crossbite. The total amount of expansion was 7 mm in all subjects. Multi-slice low-dose CT scans were taken at T0, T1, and T2. On axial CT scanned images, 4 regions of interest (ROIs) were placed along the midpalatal suture (anterior [AS ROI] and posterior [PS ROI]) and in 2 regions of palatal bone (anterior and posterior). Density was measured in Hounsfield units. The Mann-Whitney U test and Friedman analysis of variance (ANOVA) with post-hoc test were used (P <0.05). RESULTS: The densities in the AS and PS ROIs were significantly smaller than the reference bone densities before RME therapy. Both AS and PS ROIs showed significant decreases in density from T0 to T1, significant increases from T1 to T2, and no significant differences from T0 to T2. CONCLUSIONS: The effective opening of the midpalatal suture by RME in prepubertal subjects was associated with a significant decrease in sutural density. The sutural density after 6 months of retention post-RME indicated reorganization of the midpalatal suture, since it showed values similar to the pretreatment ones

Immediate and post-retention effects of rapid maxillary expansion investigated by computed tomography in growing patients

Objective: To determine by low-dose computed tomography (CT) protocol the dental and periodontal effects of rapid maxillary expansion (RME). Materials and Methods: The sample comprised 17 subjects (7 males and 10 females), with a mean age at first observation of 11.2 years. Each patient underwent expansion of 7 mm. Multislice CT scans were taken before rapid palatal expansion (TO), at the end of the active expansion phase (T1), and after a retention period of 6 months (T2). On scanned images, measurements were performed at the dental and periodontal levels. Mean differences between measurements at TO, T1, and T2 were examined through analysis of variance (ANOVA) for repeated measures with post-hoc tests. Results: All interdental transverse measurements were significantly increased at both T1 and T2 with respect to TO. In the evaluation of T0-T1 changes, periodontal measurements were significant on the buccal aspect of banded teeth with a reduction in alveolar bone thickness corresponding to the mesial (-0.5 mm; P < .05) and distal (-0.4 mm; P < .05) roots of the right first molar and to the mesial root of the left first molar (-0.3 mm; P < .05). In the evaluation of overall T0-T2 changes, the lingual bone plate thickness of both first molars was found to be significantly increased (+0.6 mm; P < .05). Conclusions: RME therapy induces a significant increase in the transverse dimension of the maxillary arch in growing subjects without causing permanent injury to the periodontal bony support of anchoring teeth discernible on CT imaging. (Angle Orthod. 2009;79:24-29.